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Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
FEATURES
* 8 Differential LVDS outputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks * Translates any single-ended input signal to LVDS with resistor bias on nCLK input * Output skew: 50ps (maximum) * Part-to-part skew: 550ps (maximum) * Propagation delay: 2.4ns (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature * Lead-Free RoHS compliant
GENERAL DESCRIPTION
The ICS85408I is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution HiPerClockSTM Chip and a member of the HiPerClock TM S family of High Performance Clock Solutions from ICS. The ICS85408I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408I provides a low power, low noise, low skew, point-to-point solution for distributing LVDS clock signals.
ICS
Guaranteed output and part-to-part skew specifications make the ICS85408I ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
OE Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
PIN ASSIGNMENT
nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q7 nQ7 OE GND VDD VDD GND VDD CLK nCLK Q0 nQ0
CLK nCLK
ICS85408I
24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View
85408BGI
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1
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Type Output Output Output Output Output Output Output Input Input Power Power Pullup Pulldown Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Positive supply pins.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 14 15 16 17, 19, 20 18, 21 Name nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 nCLK CLK VDD GND
Power supply ground. Output enable. Controls the enabling and disabling of outputs Qx, nQx. When HIGH, the outputs are enabled. When LOW, the 22 OE Input Pullup outputs are in HiZ. LVCMOS / LVTTL interface levels. 23, 24 nQ7, Q7 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Test Conditions Minimum Typical 4 51 51 4 Maximum Units pF k k pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE 0 1 Hi Z ACTIVE Outputs Q0:Q7 nQ0:nQ7 HiZ ACTIVE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1
85408BGI
nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1
Q0:Q7 LOW HIGH LOW HIGH HIGH LOW
Outputs nQ0:nQ7 HIGH LOW HIGH LOW LOW HIGH
Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential
Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
REV. A APRIL 25, 2005
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
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2
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
4.6V -0.5V to VDD + 0.5 V 10mA 15mA 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 90 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE OE OE OE VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current CLK nCLK Input Low Current CLK nCLK Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined ast VIH.
85408BGI
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3
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Test Conditions RL = 100 RL = 100 Minimum 250 1.125 -10 -1 Typical 400 1.4 Maximum 600 50 1.6 50 +10 +1 -5.5 -12 Units mV mV V mV A A mA mA
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS IOZ IOFF IOSD IOS/IOSB Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5 20% to 80% 600MHz 50 45 1.6 Test Conditions Minimum Typical Maximum 700 2.4 50 550 600 55 5 5 Units MHz ns ps ps ps % ns ns
tsk(o) tsk(pp)
tR / tF odc tPZL, tPZH
tPLZ, tPHZ Output Disable Time; NOTE 5 All parameters measured at f 622MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This paragraph is defined according with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production 5.
85408BGI
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4
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
PARAMETER MEASUREMENT INFORMATION
3.3V
VDD
SCOPE
Qx
nCLK
Power Supply +
Float GND
-
LVDS
nQx
V
CLK
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1 nQx PART 1 Qx PART 2 nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nQ0:nQ7 Q0:Q7
nCLK CLK
Pulse Width t
PERIOD
nQ0:nQ7 Q0:Q7
tPD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD
85408BGI
PROPAGATION DELAY
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5
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
VDD out
80% Clock Outputs
80% VOD
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE
VDD
VDD
out
out
DC Input
LVDS
DC Input
100
VOD/ VOD out
LVDS
out
IOSD
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT
VDD out
IOS
DC Input
LVDS
IOSB out
LVDS
IOFF
VDD
OUTPUT SHORT CIRCUIT CURRENT
85408BGI
POWER OFF LEAKAGE
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6
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V Zo = 50 Ohm
LVDS_DRIVER R1 100
CLK
nCLK Zo = 50 Ohm HiPerClockS
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
85408BGI
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7
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
85408BGI
BY
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8
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0 70C/W
200 63C/W
500 60C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85408I is: 1821
85408BGI
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9
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MS-153
85408BGI
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10
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Marking ICS85408BGI ICS85408BGI TBD TBD Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85408BGI ICS85408BGIT ICS85408BGILF ICS85408BGILFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85408BGI
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11
REV. A APRIL 25, 2005
Integrated Circuit Systems, Inc.
ICS85408I
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
REVISION HISTORY SHEET Description of Change Pin Assignment - corrected package information from 300-MIL to 173-MIL Features Section - added Lead-Free bullet. Corrected Block Diagram. Ordering Information Table - added Lead-Free par t number. Date 8/25/04 4/25/05
Rev A A
Table
Page 1 1 11
T8
85408BGI
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REV. A APRIL 25, 2005

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